During the past decade, the feature size dimensions for CMOS technologies have been continuously reduced to improve digital integration, reduce power consumption, and increase speed. In 1998 the standard CMOS process was a 180 nm process, by 2004 this had been reduced to 90 nm, to 45 nm in 2008, and 22 nm in 2012. Projecting forward it is anticipated that 10 nm processes will be available in 2016 and then 5 nm in 2020 according to the International Technology Roadmap for Semiconductors (see http://www.itrs.net/). At the same time silicon wafers have increased in diameter from 150 mm (6″), to 200 mm (8″), and by 2012 a state-of-the-art semiconductor fabrication plant would be considered as one using 300 mm (12″) wafers and today prototype (research) fabrication plants are establishing 450 mm (18″) wafer processes. However, these advancements whilst overcoming major technological hurdles in photolithography, etching, deposition, clean room quality, automated wafer handling, etc have been primarily focused to digital electronics as exemplified perhaps by microprocessors and digital memory. Today Intel's Sandy Bridge EP-8 8-core microprocessor occupies 435 mm2 and comprises 2.27 billion transistors on 22 nm linewidth clocking at 3 GHz. Similarly, today NAND flash memory devices are available based upon 20 nm processes with capacities of 16 GB and 32 GB with some manufacturers now producing on processes approaching 10 nm.
However, these achievements are not mirrored within analog circuits where these achievements of reduced device dimensions, reduced linewidths, increased digital switching speeds, material specifications, etc have caused several challenges for the analog designer, impacted performance, and reduced reproducibility of manufactured analog circuits. Such challenges include, but are not limited to, non-optimal operating points, current leakage, reduced input voltage swing, crosstalk of digital switching into analog circuit paths, and reduced linearity. Addressing these challenges via mitigating design solutions, increased control and reference circuit requirements, etc have resulted in increased use of silicon and power in order to achieve the desired performance and limited development of reconfigurable analog circuits. These adaptations for analog circuits are in many instances hampered by the lack of proper analog models as whilst our world is analog in nature the focus of CMOS electronics has been digital and digitizing the analog signal as soon as possible within the silicon circuit at rates and number of bits commensurate with the control/decision/rendering processes etc. Amongst the solution considered for addressing these issues Time-Mode Signal Processing (TMSP, also referred to as Time-Domain Signal Processing) offers a means of offsetting some of these challenges and as a result already enjoys commercial deployment in a variety of applications such as Positron Emission Topography (PTE) imaging in nuclear science, Digital Phase-Locked Loops (DPLL) in RF transmitters, and time-to-digital converters (TDC) in instrumentation, such as the Digital Storage Oscilloscope (DSO), see for example Roberts et al in “A Brief Introduction to Time-to-Digital and Digital-to-Time Converters” (IEEE Transaction on Circuits and Systems II: Express Briefs, Vol. 57, pp. 153-157).
TMSP provides a means to implement analog signal processing functions essentially in any circuit technology by exploiting one of the most basic circuit functions or elements available, namely delay. TMSP may therefore be considered, or defined, as the detection, storage, and manipulation of sampled analog information using time-difference variables. Accordingly, instead of normal circuit parameters of voltage and current TMSP uses time as the effective variable for all the computations. Accordingly, TMSP as with other signal processing techniques in manipulating the effective computational variable must be able to establish the result of addition (summation) and subtraction (difference) of two time-mode (TM) variables.
However, because time is not a physical quantity, the summation and subtraction of two time-mode (TM) variables cannot be undertaken without first transforming them into an intermediate physical quantity. Within the prior art one such approach exploited voltage as the intermediate physical quantity, see for example Ravinuthula et al in “Time-Based Arithmetic using Step Functions” (IEEE Int. Symp. Circuits and Systems, 2004, Vol. 1, pp. 305-308). Accordingly such TMSP circuits exploiting this transformation necessitate the adoption of analog components for signal processing thus forfeiting the digital advantages of today's advanced CMOS semiconductor processing and circuits for TMSP. More recently, an attempt to circumvent this problem was presented by Ying et al in “A 1.7 mW 11b 1-1-1 MASH ΛΣ Time to-Digital Converter” (IEEE Int. Solid-Slate Circuits Conference, 2011, Technical Digest, pp. 420-482) claiming a digital technique for time summation. However, as the technique is limited to the addition of a single TM variable to the phase of a running oscillator it cannot be considered a general method to addressing the requirements of summation, subtraction, etc within TMSP.
Accordingly it would be evident that a digital method to the storage, addition and subtraction of TM variables has significant benefit to providing TMSP techniques and expanding their exploitation within devices, systems, and applications. Beneficially such TMSP approaches may then exploit today's high volume, large wafer, small dimension, and high speed CMOS digital electronics. Further, the basic concepts may be transferred to essentially any digital circuit technology as they exploit delay. Accordingly, the inventors present an approach to TM variables wherein a switched delay unit is exploited and adopted such that the instantaneous phase difference between two rising signal edges can be latched and used to perform various arithmetic operations. Beneficially, the technique allows analog sampled-data signal processing to be implemented within digital circuitry.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.